PG-LDPC 부호를 위한 Soft Bit-Flipping 복호기의 파이프라인 구현

Abstract

Low-density parity-check codes are known to show higher error correcting performance than conventional algebraic codes. However, it is hard to implement in hardware when the row or column weight of them is high. In this paper, we implemented a VLSI for projective-geometry(PG) LDPC codes employing the soft bit-flipping(SBF) algorithm which has low computational and interconnection complexities. In addition to the parallel architecture, the pipelining technique and the processing unit sharing technique are employed to increase the throughput and reduce the chip area. The implemented (1057,813) 4-bit SBF decoder consumes a small area of 2.7mm2, while providing the throughput of 11.3Gbps.