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쓰레디드 메모리 모듈의 메모리 접근 지연 시간 분석 : Analyzing Memory Access Latency of Threaded Memory Modules
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 최효진 | - |
dc.contributor.author | 성원용 | - |
dc.date.accessioned | 2009-08-05T05:10:57Z | - |
dc.date.available | 2009-08-05T05:10:57Z | - |
dc.date.issued | 2009-07 | - |
dc.identifier.citation | 대한전자공학회 2009년 하계종합학술대회 2009. 7 | en |
dc.identifier.uri | http://www.ieek.or.kr | - |
dc.identifier.uri | https://hdl.handle.net/10371/6164 | - |
dc.description.abstract | Threaded memory modules can increase the number of memory requests to serve concurrently by simply modifying conventional memory modules such as DIMM (Dual In-line Memory Module). In this paper, the memory access latency of the threaded memory modules is analyzed by using a simulation method. The threaded memory modules cannot enhance the memory access performance in terms of average memory access latency, whereas it is power efficient as reported in other literature [1][2]. | en |
dc.description.sponsorship | 이 논문은 지식경제부 출연금으로 ETRI와 시스템반도체산업
진흥센터에서 수행한 ITSoC 핵심설계인력양성사업과 교육과 학기술부의 재원으로 한국학술진흥재단에서 수행하는 BK21 프로젝트의 지원을 받아 수행된 연구입니다. | en |
dc.language.iso | ko | - |
dc.publisher | 대한전자공학회 = The Institute of Electronics Engineers of Korea | en |
dc.title | 쓰레디드 메모리 모듈의 메모리 접근 지연 시간 분석 | en |
dc.title.alternative | Analyzing Memory Access Latency of Threaded Memory Modules | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | Choi, Hyojin | - |
dc.contributor.AlternativeAuthor | Sung, Wonyong | - |
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