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An 8 x 8 nRERL serial multiplier for ultra-low-power applications

DC Field Value Language
dc.contributor.authorLim, Joonho-
dc.contributor.authorKim, Donggyu-
dc.contributor.authorKang, Sangcheol-
dc.contributor.authorChae, Soo-Ik-
dc.date.accessioned2010-04-01T01:07:09Z-
dc.date.available2010-04-01T01:07:09Z-
dc.date.issued2000-01-
dc.identifier.citationProc. of ASP-DAC'98, pp.35-36en
dc.identifier.isbn0780359747-
dc.identifier.urihttps://hdl.handle.net/10371/62268-
dc.description.abstractAn 8 x 8-b nRERL serial multiplier is
implemented in a 0.6- m n-well 3-metal CMOS pro-
cess. nRERL (nMOS Reversible Energy Recov ery
Logic) is a new reversible adiabatic logic circuit, which
can be operated at the leakage-current lev el for ultra-
low-energy applications. Measurement results show ed
that the nRERL serial multiplier consumed only 0.9
% of the energy dissipation of the static CMOS one
at the operating frequency 100 kHz at 5V, where its
adiabatic and leakage losses were about equal.
en
dc.description.sponsorshipThe test chip was fabricated with the help of IDEC
program of KAIST, Taejon, Korea. This paper was sup-
ported by NON DIRECTED RESEARCH FUND, Korea
Research Foundation,throught Inter-university Semicon-
ductor Research Center, Seoul National University, Seoul,
Korea, from 1996 to 1999.
en
dc.language.isoenen
dc.publisherIEEEen
dc.titleAn 8 x 8 nRERL serial multiplier for ultra-low-power applicationsen
dc.typeConference Paperen
dc.contributor.AlternativeAuthor임준호-
dc.contributor.AlternativeAuthor김동규-
dc.contributor.AlternativeAuthor강상철-
dc.contributor.AlternativeAuthor채수익-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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