Browse

Implementation of a simple 8-bit microprocessor with reversible energy recovery logic

Cited 0 time in Web of Science Cited 0 time in Scopus
Authors
Kim, Seokkee; Chae, Soo-Ik
Issue Date
2005-05
Publisher
ACM
Citation
Conference On Computing Frontiers, pp.421-426
Keywords
MicroprocessornMOS Reversible Energy Recovery Logic (nRERL)Clocked Power Generator (CPG)Phase SchedulingReversibility Breaking
Abstract
We describe a simple 8-bit adiabatic microprocessor implemented
with nMOS reversible energy recovery logic (nRERL) [1]. The
implemented adiabatic microprocessor supports only a subset of
the DLX instruction set architecture [15] in order to be fitted into
a limited silicon area, and is integrated with an energy-efficient 6-
phase clocked power generator (CPG). Phase scheduling was
employed to reduce the number of the buffers required in the
adiabatic microprocessor. Furthermore, reversibility breaking with
self-energy recovery circuits (SERCs) was also employed to
reduce energy consumption as well as circuit complexity by. The
8-bit microprocessor core and its on-chip 6-phase CPG were
implemented in 0.18-μm CMOS technology. The former and the
latter occupied 2.62 x 2.03 mm2 and 1.0 x 0.6 mm2, respectively.
From the measurements, we have found that its minimum power
consumption is 7.5μW at Vdd =1.8V and f=880kHz.
Language
English
URI
http://hdl.handle.net/10371/62274
Files in This Item:
There are no files associated with this item.
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse