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Functional modeling techniques for efficient SW code generation of video codec applications
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, SangIl | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.contributor.author | Jerraya, Ahmed. A. | - |
dc.date.accessioned | 2010-04-01T01:23:04Z | - |
dc.date.available | 2010-04-01T01:23:04Z | - |
dc.date.issued | 2006-01 | - |
dc.identifier.citation | Asia and South Pacific Design Automation Conference, pp.74-85 | en |
dc.identifier.isbn | 0780384518 | - |
dc.identifier.uri | https://hdl.handle.net/10371/62277 | - |
dc.description.abstract | Architectures with multiple programmable cores
are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multiple video standards and a shorter time-to-market. To find an efficient SW code for the multiple core architecture for a video codec application, it is very important to easily explore the design space by generating a SW code automatically from its functional model. We introduce Abstract Clock Synchronous Model (ACSM) for functional modeling of video codec applications. The ACSM can easily represent both parallelism and conditionals, which are common in video codec applications. By applying ACSM to an H.264 baseline decoder on single core architecture, we reduced the execution time and the number of external memory accesses by 32 % and 46 % respectively compared to traditional dataflow model. | en |
dc.description.sponsorship | The authors are grateful to Xavier Guerin, Paul Amblard,
Frédéric Pétrot and Nacer-Eddine Zergainoh from TIMA laboratory for their inputs on this paper. This work was supported by ITSoC Project and Brain Korea 21 Program. | en |
dc.language.iso | en | - |
dc.publisher | ACM | en |
dc.title | Functional modeling techniques for efficient SW code generation of video codec applications | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | 한상일 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
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