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High performance IPC hardware accelerator and communication network for MPSoCs
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- Authors
- Issue Date
- 2008-11
- Citation
- International SoC Design Conference, Vol.3 CDC Session pp.21-22
- Keywords
- MPSoC ; IPC ; synchronization ; multimedia ; H.264
- Abstract
- In this paper, we explain a configurable IPC module
for multimedia MPSoCs, which was implemented in a MPW chip
that include three ARM7 CPU cores. According to the test results
for an M-JPEG and a H.264 decoder, its IPC synchronization
overheads are not more than 1% when the synchronization
period is about 5000 cycles.
- Language
- English
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