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시간 제약을 고려하는 플립칩 설계에서 Boolean SAT를 활용한 라우팅 기법 : Timing constrained routing in IO area flip chip design based on Boolean Satisfiability
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 김태환 | - |
| dc.contributor.author | 전형준 | - |
| dc.date.accessioned | 2010-05-10T04:06:59Z | - |
| dc.date.available | 2010-05-10T04:06:59Z | - |
| dc.date.copyright | 2010 | - |
| dc.date.issued | 2010 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000033502 | kog |
| dc.identifier.uri | https://hdl.handle.net/10371/64990 | - |
| dc.description | 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2. | ko |
| dc.format.extent | vii, 51 장 | ko |
| dc.language.iso | ko | ko |
| dc.publisher | 서울대학교 대학원 | ko |
| dc.subject | 플립칩 라우팅 | ko |
| dc.subject | flip chip routing | ko |
| dc.subject | 시간 제약 | ko |
| dc.subject | timing constrain | ko |
| dc.subject | Boolean SAT | ko |
| dc.subject | Boolean SAT | ko |
| dc.title | 시간 제약을 고려하는 플립칩 설계에서 Boolean SAT를 활용한 라우팅 기법 | ko |
| dc.title.alternative | Timing constrained routing in IO area flip chip design based on Boolean Satisfiability | ko |
| dc.type | Thesis | - |
| dc.contributor.department | 전기. 컴퓨터공학부 | - |
| dc.description.degree | Master | ko |
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