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Low-Power Implementation of a High-Throughput LDPC Decoder for IEEE 802.11n Standard
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Cho, Junho | - |
| dc.contributor.author | Shanbhag, Naresh R. | - |
| dc.contributor.author | Sung, Wonyong | - |
| dc.date.accessioned | 2010-09-06T06:03:04Z | - |
| dc.date.available | 2010-09-06T06:03:04Z | - |
| dc.date.issued | 2009-10 | - |
| dc.identifier.citation | IEEE Workshop on Signal Processing Systems, 7-9 Oct. 2009, Tampere, Finland, pp. 40-45 | en |
| dc.identifier.issn | 1520-6130 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/69746 | - |
| dc.description.abstract | A flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. A serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VOS) and reduced-precision replica (RPR) are applied to the decoder. Power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology. | en |
| dc.language.iso | en | en |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
| dc.title | Low-Power Implementation of a High-Throughput LDPC Decoder for IEEE 802.11n Standard | en |
| dc.type | Conference Paper | en |
| dc.contributor.AlternativeAuthor | 조준호 | - |
| dc.contributor.AlternativeAuthor | 성원용 | - |
| dc.identifier.doi | 10.1109/SIPS.2009.5336223 | - |
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