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Fractional rate dataflow model for efficient code synthesis

DC Field Value Language
dc.contributor.authorOh, Hyunok-
dc.contributor.authorHa, Soonhoi-
dc.date.accessioned2009-08-21T04:15:35Z-
dc.date.available2009-08-21T04:15:35Z-
dc.date.issued2004-05-
dc.identifier.citationJournal of VLSI Signal Processing, 2004, vol. 37, no. 1, pp. 41-51en
dc.identifier.issn0922-5773 (print)-
dc.identifier.issn1573-109X (online)-
dc.identifier.urihttps://hdl.handle.net/10371/7437-
dc.description.abstractAutomatic code synthesis from dataflow program graphs is a promising high-level design methodology
for rapid prototyping of multimedia embedded systems. Memory efficient code synthesis from dataflow models has
been an active research subject to reduce the gap in terms of memory requirements between the synthesized code
and the hand-optimized code. However, existent dataflow models have inherent difficulty of efficiently handling
data structures. In this paper, we propose a new dataflow extension called fractional rate dataflow (FRDF) in which
fractional number of samples can be produced and consumed. In the proposed FRDF model, a constituent data type
is considered as a fraction of the composite data type. Existent integer rate dataflow models can be easily extended
to incorporate the fractional rates without loosing analytical properties. In this paper, the SDF model is extended
to include FRDF, which can reduce the buffer memory requirements significantly, up to 70%, for some multimedia
applications. Extended SDF model with fractional rate has been implemented in our system design environment
called PeaCE(Ptolemy extension as Codesign Environment).
en
dc.description.sponsorshipThis research is supported by National Research
Laboratory Program (number M1-0104-00-0015) and
BrainKorea 21 program. The RIACT at Seoul National
University provides research facilities for this study.
en
dc.language.isoenen
dc.publisherSpringer Verlagen
dc.subjectcode synthesisen
dc.subjectsynchronous dataflow (SDF)en
dc.subjectmemory optimizationen
dc.subjectmultimediaen
dc.titleFractional rate dataflow model for efficient code synthesisen
dc.typeArticleen
dc.contributor.AlternativeAuthor오현옥-
dc.contributor.AlternativeAuthor하순회-
dc.identifier.doi10.1023/B:VLSI.0000017002.91721.0e-
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