S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Computer Science and Engineering (컴퓨터공학부) Journal Papers (저널논문_컴퓨터공학부)
A Retargetable Parallel-Programming Framework for MPSoC
- Kwon, Seongnam; Kim, Yongjoo; Jeun, Woo-Chul; Ha, Soonhoi; Paek, Yunheung
- Issue Date
- ACM Trans. Des. Autom. Electron. Syst. 13, 3, Article 39
- Embedded software; multiprocessor system on chip; software generation; design-space exploration; parallel-programming
- As more processing elements are integrated in a single chip, embedded software design becomes
more challenging: It becomes a parallel programming for nontrivial heterogeneous multiprocessors
with diverse communication architectures, and design constraints such as hardware cost,
power, and timeliness. In the current practice of parallel programming with MPI or OpenMP, the
programmer should manually optimize the parallel code for each target architecture and for the
design constraints. Thus, the design-space exploration of MPSoC (multiprocessor systems-on-chip)
costs become prohibitively large as software development overhead increases drastically. To solve
this problem, we develop a parallel-programming framework based on a novel programming model
called common intermediate code (CIC). In a CIC, functional parallelism and data parallelism of
application tasks are specified independently of the target architecture and design constraints.
Then, the CIC translator translates the CIC into the final parallel code, considering the target
architecture and design constraints to make the CIC retargetable. Experiments with preliminary
examples, including the H.263 decoder, show that the proposed parallel-programming framework
increases the design productivity of MPSoC software significantly.
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