Dynamic Voltage Scheduling with Buffers in Low-Power Multimedia Applications

Abstract

Power-efficient design of multimedia applications becomes more important as they are used increasingly in many embedded systems. We propose a simple dynamic voltage scheduling technique which suits multimedia applications well and, in case of soft real-time applications, allows all idle intervals of the processor to be fully exploited by using buffers. Our main theme is to determine the minimum buffer size to maximize energy saving in three cases: (i) single-task, (ii) multiple-subtask and (iii) multi-task. We also present a technique of adjusting task deadlines for further reducing energy consumption in the multiple-subtask and multi-task cases. Unlike other DVS techniques using buffers, we guarantee to meet the real-time latency constraint. Experimental results show that the proposed technique does indeed achieve significant power reduction in real-world multimedia applications.