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Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jung, Hyunuk | - |
dc.contributor.author | Lee, Kangnyoung | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.date.accessioned | 2009-08-28T05:06:57Z | - |
dc.date.available | 2009-08-28T05:06:57Z | - |
dc.date.issued | 2002-08 | - |
dc.identifier.citation | IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 10, No. 4, pp. 423-428, 2002 | en |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://hdl.handle.net/10371/7987 | - |
dc.description.abstract | Abstract—This paper concerns automatic hardware synthesis
from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow graph represents a hardware library module that contains a synthesizable VHDL code. Our proposed technique automatically synthesizes a clever control structure, cascaded counter controller, that supports asynchronous interaction with outside modules while efficiently implementing the synchronous dataflow semantics of the graph at the same time. Through comparison with previous works with some examples, the novelty of the proposed technique is demonstrated. | en |
dc.description.sponsorship | This work
was supported by the National Research Laboratory (NRL) Grant and the Brain Korea 21 Project. The RIACT at Seoul National University provides research facilities for this study. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.subject | Data flow graph | en |
dc.subject | synchronous data flow | en |
dc.subject | system level design | en |
dc.subject | VHDL | en |
dc.title | Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 정현욱 | - |
dc.contributor.AlternativeAuthor | 이강녕 | - |
dc.contributor.AlternativeAuthor | 하순회 | - |
dc.identifier.doi | 10.1109/TVLSI.2002.807765 | - |
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