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Transformation and VHDL Code Generation from Coarse-grained Dataflow Graph
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Moonwook | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.date.accessioned | 2009-09-17 | - |
dc.date.available | 2009-09-17 | - |
dc.date.issued | 1999-01-21 | - |
dc.identifier.uri | https://hdl.handle.net/10371/9633 | - |
dc.description.abstract | This paper discusses how we generate VHDL codes for DSP applications described in dataflow graphs. Because the generated VHDL code implements the details of the control structure, we can easily transform it into a running circuit without any modifications, using logic synthesis tools. To improve the quality of the synthesized circuit we apply some graph transformation techniques to the original dataflow graph. We mainly consider coarse-grained dataflow graphs in which each node corresponds to an IP component of considerable size. The proposed facility is very useful for dataflow graph based high level design tools, including our codesign framework PeaCE (Ptolemy extension as Codesign Environment). | en |
dc.language.iso | en | - |
dc.publisher | 한국정보과학회 = Korea Informaion Science Society | en |
dc.subject | VHDL Code Generation | en |
dc.subject | Dataflow Graph Transformation | en |
dc.subject | EDA | en |
dc.title | Transformation and VHDL Code Generation from Coarse-grained Dataflow Graph | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 오문욱 | - |
dc.contributor.AlternativeAuthor | 하순회 | - |
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