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Showing results 1 to 5 of 5

Issue Date	Title / Author(s) / Citation	File
2009	Leakage Power Reduction of Functional Units in Processors having Zero-Overhead Loop Counter Park, Hanmin; Paek, Jong Kyung; Lee, Jinho; Choi, Kiyoung 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), pp.492-495	DOI
2019-01	Cell Division: Weight Bit-Width Reduction Technique for Convolutional Neural Network Hardware Accelerators Park, Hanmin; Choi, Kiyoung 24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019), pp.286-291	DOI
2019-06	Acceleration of DNN Backward Propagation by Selective Computation of Gradients Lee, Gunhee; Park, Hanmin; Kim, Namhyung; Yu, Joonsang; Jo, Sujeong; Choi, Kiyoung PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), pp.1-16	DOI
2021	GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent Kim, Heesu; Park, Hanmin; Kim, Taehyun; Cho, Kwanheum; Lee, Eojin; Ryu, Soojung; Lee, Hyuk-Jae; Choi, Kiyoung; Lee, Jinho 2021 27TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA 2021), Vol.2021-February, pp.249-262	DOI
2022-07	ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator Kim, Namhyung; Park, Hanmin; Lee, Dongwoo; Kang, Sungbum; Lee, Jinho; Choi, Kiyoung IEEE Transactions on Computers, Vol.71 No.7, pp.1537-1550	DOI