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Showing results 1 to 6 of 6

Issue Date	Title / Author(s) / Citation	File
2001	Time-to-Digital Converter를 이용한 Cable Tester에 있어서 오차의 자동 보정에 관한 연구 양성욱	link
2007	PVT Tolerant and Fast Locking 하는 ADPLL의 설계 지한규	link
2010	Open-loop 모드에서 동작하는 Delay-Locked Loop를 사용한 고해상도 시간-디지털 변환기 이형민	link
2014-02	Design of Digital PLL/CDR with Advanced Digital Controller 류시강	view file
2015-04	A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.867-881	DOI
2018-03	A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation Choi, Woo Seok; Shu, Guanghua; Talegaonkar, Mrunmay; Liu, Yubo; Wei, Da; Benini, Luca; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.53 No.3, pp.884-895	DOI