Electrical channel formed by the tunneling electroplating

Abstract

The extreme miniaturization of semiconductor devices in recent years has exposed the intrinsic limitations of the characteristics of silicon materials in conventional device structures. In light of efforts to circumvent these problems, researchers are trying to utilize single atoms or monolayer film in FET (field-effect transistor) channels in addition to using alternative materials such as III-V semiconductors, CNT (carbon nanotube), or graphene. In this thesis, a novel metal channel device structure as well as its operation method and fabrication process will be proposed. A process flow is proposed and the test pattern is produced accordingly. It has been developed and demonstrated a new manufacturing method dubbed tunneling electroplating, which is used to construct metal layers of nanometer-order thickness on dielectric materials. An analysis of a metal-electrolyte-metal (MEM) structure is conducted to create the devised metal channel device efficiently. The analysis result is then combined with information from the reduction potential and target ion energy level in an energy band diagram for a better electrical analysis of the electroplating process. Metal layers of the dielectric material with a thickness on the nanometer order are constructed in the forms of electrolyte-oxide-silicon (EOS) and electrolyte-metal-oxide-silicon (EMOS) structures, demonstrating that the tunneling current through the oxide film via an electrolyte is limited by the electric potential across the oxide film. The radical increase in the tunneling current in repeated electric characterizations of the EOS structures is found to be caused by the reduction of the effective oxide thickness due to hydrogen ions (protons) penetrating into the oxide films. A new oxide layer recovery method which emits protons periodically is also proposed, and it is confirmed that, with this method, metal layers of nanometer-order thickness can be formed on the oxide surface without a breakdown of the dielectric layer. For an enhancement of the oxide adhesion of metal particles produced in the upper dielectric layer during a tunneling electroplating process, the devices are dipped into APTES (3-aminopropyltriethoxysilane) as a SAM (self-assembled monolayer) treatment. The electrolyte, source, drain and substrate currents through the test patterns during the tunneling electroplating process are also analyzed and the metal layer formation and channel completion mechanisms are clarified, including what is termed a self-limitation method that prevents the thickness of the metal layer on the oxide films from increasing. This tunneling electroplating method can realize the room-temperature manufacturing of metal layers for FET channel purposes. Because it is compatible with existing CMOS process, it can be easily applied to mass production through additional integration with current semiconductor chips. The applicability of the devised tunneling electroplating process is quite broad in many applications, such as nanometer-order transistor- or metal-based sensors.