GaN Non-uniform Distributed Power Amplfier Design for enhanced power and efficiency

Abstract

In this thesis, I propose a non-uniform distributed power amplifier design (NDPA) for enhanced power and efficiency using a commercial gallium nitride (GaN) semiconductor process to realize a wideband power amplifier which is an essential component of electronic warfare systems such as active electronically scanned array (AESA) radars and electronic jammers. First, large signal modeling including thermal effect which is the basis of the NDPA design is carried out. DC and RF measurements are performed on a 6×125 μm GaN high-electron-mobility transistor (HEMT) and the measured data are fitted to Angelov-based model equations. Also, a thermal model equivalent circuit is constructed by extracting the thermal resistance through the pulsed IV measurement, and the RF Ids and the DC Ids are separately modeled to reflect the frequency dispersion phenomenon. The thermal resistance is measured by thermally pasting the device on the same jig so as to be similar to the actual monolithic microwave integrated circuit (MMIC) measurement environment. For the model verification, a 6 ~ 18 GHz, 8.1 W uniform distributed power amplifier (DPA) MMIC is designed and compared with the measurement. The output power characteristics of DPA which is designed by in-house GaN HEMT large signal model show better agreement with the measured value than those by the model provided by the foundry. Second, to increase output power in the wideband, the previous NDPA design is modified. The conventional NDPA design method assumes that the drain-source capacitance (Cds) is absorbed in the transmission line. However, the larger the transistor size is and the higher the frequency, the more its effect cannot be ignored. Also, in the process of arranging the drain line impedance so that each transistor in the NDPA has the optimum output load impedance (Ropt), the first drain line impedance usually becomes greater than 100 Ω, which causes a problem that the metal line width is too narrow to be fabricated by a commercial process. The conventional NDPA design uses a large-sized transistor at the first section to avoid this limitation so that increased gate-to-source capacitances and drain-to-source capacitances degrade power gain and output power at high frequencies. In this study, an NDPA design is proposed that reflects the drain-source capacitance. After the Cds is added to the existing drain line impedance to make an equivalent model with the π-type line, the line impedance is readjusted to have the Ropt at the center frequency. By applying this design method to the NDPA, the average output power could be improved by 0.4 dB at 6 ~ 18 GHz than the conventional method. Besides, instead of using a large-sized transistor at the first section in the NDPA, a method of halving the characteristic impedance (Zo) by doubling the phase of the drain line is proposed. As a result of analyzing loss due to the increase of the line length, the high-frequency loss is reduced compared with the conventional method, and power gain and the output power characteristics close to the ideal NDPAs can be obtained. Meanwhile, to further increase output power, NDPAs are required to be power-combined. In this case, there has been a problem that due to long gate/drain lines, the chip size becomes large. In this work, a compact power combining scheme is proposed that shares the drain lines of each NDPA. Sharing the drain lines reduces the chip size and loss by decreasing the number of impedance transformers and power combiners required for power combining. Moreover, it reduces the line length by half if the line impedance is kept as the same impedance as before sharing the drain line. Because this approach increases the compactness in the power combining, it contributes to increasing the power density of NDPAs. Besides, the shared drain line allows the drain-to-source resistance (Rds) of each transistor to be connected in parallel, thus providing additional benefit to improve the output return loss when using large size devices. The proposed design method is applied to NDPA MMICs using commercial 0.25 μm GaN MMIC process. A 2-way, 2-stage, and 8-section NDPA MMIC is designed using 6×125 μm GaN HEMT devices. As a result, the fabricated MMIC shows the linear gain of 16.8 ~ 21.8 dB, the continuous wave (CW) output power (Pout) of 21 W and the power added efficiency (PAE) of 19.2 % at 6 ~ 18 GHz. In particular, it accomplishes the highest power density of 1.9 W/mm2 in similar broadband frequency bands. A 4-way, 2-stage NDPA MMIC is also designed and fabricated by extending the proposed power combining structure. Because the number of power combining is increased to 4, a 6×75 μm GaN HEMT device is used instead of a 6×125 μm. It shows the linear gain of 13 ~ 17 dB, the average CW Pout of 20.8 W and the average PAE of 14 % at 6 ~ 18 GHz. In particular, the average Pout of 26 W is measured at the pulsed power measurement, and the maximum Pout of 40 W is obtained at 13 GHz. The proposed compact power combining scheme allows four NDPAs to be power-combined, resulting in the highest output power characteristics in similar broadband frequency bands. From the above results, the validity and effectiveness of the proposed NDPA design method can be verified. Third, an NDPA design for enhanced power efficiency is proposed. To obtain high efficiency in the NDPA, power gain needs to be increased. Varying the gate line termination resistance (Rgt) in the NDPA can increase power gain according to frequencies. When designing an NDPA, drain line termination resistors are usually eliminated to prevent output power and efficiency from degrading due to power loss through termination loads. In this case, the reflected wave components of the gate line and the drain line, which have been neglected are increased according to the magnitude of Rgt as shown in the power gain expression of the distributed amplifier theory, thereby forming ripples of power gain depending on the frequency. Using these ripples, power efficiency can be improved when the power gain is increased at a desired frequency. However, when the NDPA MMIC is fabricated using the proposed idea, the Pout and PAE of NDPA are only increased by 0.22 dB and 1.2%, respectively. Simulation results show that the peak power gain decreases when the NDPA operates under low Rgt due to gate line loss. The reduced peak gain degrades NDPAs PAE. To compensate for this degradation, an inductive line is inserted in front of the Rgt to improve the input return loss. On the other hand, as the operating frequency increases in the NDPA, the Ropt for determining the drain line impedance is observed to increase. As a result, the maximum output power cannot be obtained according to the frequency, and mismatch occurs, which degrades the overall power efficiency. To make up for this mismatch, the four drain line impedances of the front end are designed according to the Ropt of 6 GHz, and the four drain line impedances of the rear end are designed according to the Ropt of 18 GHz. This rearrangement of the drain line impedances is because the transistors and drain lines on the rear end of the NDPA are more susceptible to high frequencies. Simulation results show that the proposed design method improves Pout by 0.3 dB and PAE by 2.8% at 6 ~ 18 GHz. The proposed design concepts are applied to the second fabrication of the NDPA MMIC. As a result, the average Pout is 39.8 dB, and the average PAE is 20% at 6 ~ 18 GHz. When the Rgt is tuned according to the frequency, there is the Pout improvement of 0.3 dB and the PAE improvement of 2.3%. Notably, at 13 GHz, the Pout is improved by 1.24 dB and the PAE is increased by 6.8% when the Rgt is optimally tuned. In conclusion, the insertion of inductive line and drain line impedance re-design considering frequency-dependent optimum load impedance improve the average Pout of 0.9 dB and the average PAE of 6.5% compared to the first MMIC in operating frequency band. Also, the PAEs increment when the Rgt is optimally tuned is improved by 1.1%. When compared to the conventional NDPA using the same process, the proposed efficiency enhanced design increases the PAE by 3%. It is verified that the proposed idea contributes to the power efficiency improvement of the NDPA. Then an additional circuit is designed for automatically switching the Rgt depending on the frequency. A part of the input signal is taken in a 10 dB coupler and passed through a Wilkinson power divider to allow one signal to be used to sense the input RF power and the other to enter the power detector. Then the same circuit as the gate lines of the NDPA is separately made using MMIC test patterns and shunt-connected to the front of the power detector. This circuit is to reproduce the standing wave caused by the mismatch of the gate line termination in the NDPA according to frequencies, so that the power detector can read the voltage swing generated here, so that frequency-dependent (or, gain-ripple dependent) voltage values are generated. If generated voltages are amplified by the op-amp and then input to the comparator and compared with the reference voltage, the desired voltage can be generated so that the gate line termination resistance is switched in the direction that the Pout of the NDPA is higher at the desired frequency. Finally, the generated voltage enters the gate port of the variable resistance transistor. As a result of the experiment, it is confirmed that the NDPA operates at the ideal Rgt value in the frequency band where the power efficiency difference is large according to the Rgt, and the reduction of PAE due to the voltage generation error is only average 0.1 % in the operating frequency band. Therefore, it is verified that the efficiency of NDPA can be improved through the programmable gate line termination resistance switching technique and the drain line impedance re-design considering frequency-dependent Ropt. In this thesis, the NDPA design method is improved, and a novel NDPA is implemented with average output power of 20 W or more and power density of 1.9 W/mm2 at 6 ~ 18 GHz. The newly proposed programmable gate line termination resistance switching technique accomplishes a wideband power amplifier with an average output power of 10 W and an average power added efficiency of 20% or more at 6 ~ 18 GHz.