Characterization of Trap Generated By Process and Cycling Stress in 26 nm NAND Flash Memory

Abstract

Trap in 26 nm NAND flash memory was characterized in terms of bit-line (BL) current fluctuation (∆IBL), extraction of trap position in 3-D space (xT, yT, and zT) of the tunneling oxide and trap energy (Et). Especially, percolation path could be identified and accurate zT could be obtained, using the states of adjacent cells. Then, ∆IBL, S_I/I_BL^2, capture (τc) and emission times (τe) of RTN were measured before and after cycling stress, respectively. With cycling stress, S_I/I_BL^2 and ∆IBL were increased significantly. τc and τe of RTN after cycling stress are shorter by about 2~3 times than those of RTN generated by process stress. With the program (P) and erase (E) states of adjacent cells, ∆IBL and corner frequency (fc) of Lorentzian spectrum are changed. Using measured ∆IBL and extracted τc and τe with 4 different modes (P/P, P/E, E/P, E/E), we calculated τ and fc, and extracted the position of a trap in the channel width direction with ∆IBL and simulated data. The calculated data showed excellent agreement with measured spectra. Finally, trap was characterized with the method charge pumping method.