Novel program method of string select transistors for layer selection in channel-stacked NAND flash memory

Abstract

In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage (V-th) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted V-th values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the V-th values of SSTs/DSSTs are set to the targeted V-th values by the new methods and SSTs with extremely narrow V-th distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the V-th values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.