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Making DRAM Stronger Against Row Hammering

Cited 0 time in Web of Science Cited 58 time in Scopus
Authors

Son, M.; Park, H.; Ahn, J.; Yoo, S.

Issue Date
2017
Publisher
Proceedings - Design Automation Conference
Citation
Proceedings - Design Automation Conference, Vol.Part 128280, p. 55
Abstract
Modern DRAM suffers from a new problem called row hammering. The problem is expected to become more severe in future DRAMs mostly due to increased inter-row coupling at advanced technology. In order to address this problem, we present a probabilistically managed table (called PRoHIT) implemented on the DRAM chip. The table keeps track of victim row candidates in a probabilistic way and, in case of auto-refresh, the topmost entry is additionally refreshed thereby mitigating the row hammering problem. Our experiments with PARSEC benchmark and synthetic traces show that PRoHIT outperforms the state-of-The-Art method, PARA, by 35.7% (PARSEC) in terms of the reduction ratio of row-hammer cases. Our proposed method also shows constantly superior performance to PARA for synthetic traces. © 2017 ACM.
ISSN
0146-7123
URI
https://hdl.handle.net/10371/192905
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