28.5 A 900μW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces

Abstract

To secure sufficient timing margins, despite ever-increasing data rates, advanced DRAM interfaces use quadrature clocks, which run internally at a quarter-rate frequency, ftextQCLk. The top of Fig. 28.5.1 shows a conventional clock-distribution scheme: a DLL in the middle of the peripheral distributes the quadrature clocks, StextINx where x=I, Q, IB, QB to all TXs that may be more than a few millimeters away. The fundamental problem with this conventional scheme is that it requires excessive power to distribute four (or at least two) high-frequency clocks over long distances across the chip. With ftextQCLK=2textGHz, the clock distribution power consumption reaches tens of milliwatts and will continue to increase proportionally to ftextQCLK for future standards. Moreover, the quadrature relationship between StextINx is degraded as well, thus a quadrature-error corrector (QEC) can be used before each TX. Polyphase-filter- or analog-DLL-based QECs have issues with accuracy and area. Recently, digital DLL-based QECs [1-4] overcome these problems, but still have many disadvantages. (1) DLL-based ones cannot filter input jitter: the RMS jitter of the quadrature clocks at each TX should be less than 6textmUI, hence the jitter-filtering capability becomes more important as ftextQCLk increases. (2) They consume large power when operating at ftextQCLK: the QEC in [1] consumes 8textmW at ftextQCLK of 2.3GHz. (3) They use DTCs to detect quadrature errors, the range of ftextQCLK is limited to that of the DTC. (4) Their outputs, StextOUTx have a 50% duty-cycle (DC), an additional 25%-DC converter is required before the serializer at each TX.