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Low-Cost Packaging of 300 GHz Integrated Circuits With an On-Chip Patch Antenna
Cited 12 time in
Web of Science
Cited 12 time in Scopus
- Authors
- Issue Date
- 2019-11
- Citation
- IEEE Antennas and Wireless Propagation Letters, Vol.18 No.11, pp.2444-2448
- Abstract
- Placing a 300 GHz on-chip patch antenna in a low-cost quad-flat no-lead (QFN) package using materials based on silica microparticles dispersed in an epoxy matrix can improve the antenna performance. Full-wave simulations of a rectangular patch antenna, compliant with the metal stack and design rules of a 65 nm complementary metal-oxide-semiconductor (CMOS) process, show 13% radiation efficiency, 1 dB peak antenna gain, and 7 GHz -10 dB vertical bar S-11 vertical bar bandwidth increases when the thickness of packaging material over the antenna is similar to lambda/3. When placed in a QFN package, 276 GHz CMOS signal generators with the same on-chip antenna show the effective isotropic radiated power similar to 6 dB higher than that of unpackaged. This improvement is partly attributed to the antenna performance enhancement and demonstrates that it is possible to package 300 GHz integrated circuits with an on-chip patch antenna using a low-cost technique.
- ISSN
- 1536-1225
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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