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A mixed-level virtual prototyping environment for SystemC-based design methodology

Cited 1 time in Web of Science Cited 3 time in Scopus
Authors
Park, Sanggyu; Yoon, Sangyong; Chae, Soo-Ik
Issue Date
2009
Publisher
Elsevier
Citation
Microelectronics Journal. 40(7) 1082-1093.
Keywords
SystemCTransactionlevelmodelChannelArchitecturetemplateVirtual prototype
Abstract
Weproposeaflexiblemixed-levelvirtualprototypingenvironment,wheremodelsindifferent
abstraction levelssuchastransactionlevel,register-transferlevel,andsoftwarelevelcanbeco-
simulatedtogether.Intheproposedenvironment,thedesignersshouldcaptureatransactionlevel
systemmodelbeforehardware–softwarepartitioning,fromwhichmixed-levelvirtualprototyping
models canberefinedwithpre-definedandpre-verifiedcommunicationprimitives.Weexplainseveral
techniquesemployedintheenvironmentsuchasIDportsforsoftwaretemplateefficiency,abstraction
adaptersinSystemCformixedlevelsimulation,andtrace-drivensimulationforfasterperformance
evaluation.Moreover,transactionleveldescriptionsinSystemCcanbecompiledandexecutedas
softwaretogetherwiththeDEOS,whichisanoperatingsystemthatprovidesSystemCAPIs.We
comparedthesimulationspeedofseveralmixed-levelvirtualprototypesofaH.264decodertoshowthe
effectiveness oftheproposedenvironment.
ISSN
0026-2692
Language
English
URI
http://hdl.handle.net/10371/21264
DOI
https://doi.org/10.1016/j.mejo.2008.05.010
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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