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상위단계 합성에서의 타이밍 최적화를 위한 버퍼 삽입 활용
Utilization of Buffer Insertion for Timing Optimization in High-level Synthesis

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Authors
박상도
Advisor
김태환
Issue Date
2009
Publisher
서울대학교 대학원
Keywords
타이밍Timing상위 단계 합성High-Level Synthesis버퍼 삽입buffer insertion설계 흐름Physical designdesign flow
Description
학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2009.8.
Language
Korean
URI
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000038751

http://hdl.handle.net/10371/44669
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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