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(An)Alternating edge-sampling clock and data recovery circuit for loop characteristic stabilization : 루프특성 안정화를 위한 교차 천이검출 클럭데이터 복원회로
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- Authors
- Advisor
- 정덕균
- Issue Date
- 2004
- Publisher
- 서울대학교 대학원
- Keywords
- CMOS 직렬 송수신기 ; Cmos serial link transceiver ; 지터 검출 회로 ; Jitter-estimation circuitry ; 위상 검출기 ; Phase detector (pd) ; 교차 천이 검출 ; Alternating-edge sampling (aes) method ; 클록-데이터 복원 회로 ; Clock/data recovery (cdr) ; Phase-locked loop (pll) ; Sampler ; Voltage-controlled oscillator (vco) ; Pre-emphasis ; Inductive peaking
- Description
- Thesis (doctoral)--서울대학교 대학원 :전기·컴퓨터공학부,2004.
- Language
- English
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000054458
https://hdl.handle.net/10371/45831
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