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(A) study on design of all-digital phase-locked loop : All-digital PLL 설계에 관한 연구
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- Authors
- Advisor
- 정덕균
- Issue Date
- 2009
- Publisher
- 서울대학교 대학원
- Keywords
- 클럭-데이터 복원기 ; ADPLL ; 주파수합성기 ; Clock-and-Data Recovery ; 지터 ; Frequency Synthesizer ; 위상잡음 ; Jitter ; Phase noise ; Time-to-Digital Converter ; Digitally-Controlled Oscillator
- Description
- Thesis(doctors) --서울대학교 대학원 :전기· 컴퓨터공학부,2009.8.
- Language
- English
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000038196
https://hdl.handle.net/10371/46839
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