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A 1.35GHz All-Digital Fractional-N PLL with Adaptive Loop Gain Controller and Fractional Divider
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Deok-Soo | - |
dc.contributor.author | Song, Heesoo | - |
dc.contributor.author | Kim, Taeho | - |
dc.contributor.author | Kim, Suhwan | - |
dc.contributor.author | Jeong, Deog-Kyoon | - |
dc.date.accessioned | 2010-06-29T23:58:53Z | - |
dc.date.available | 2010-06-29T23:58:53Z | - |
dc.date.issued | 2009-11 | - |
dc.identifier.citation | IEEE Asian Solid-State Circuits Conference, November 16-18, 2009 / Taipei, Taiwan, pp. 161-164 | en |
dc.identifier.uri | https://hdl.handle.net/10371/68016 | - |
dc.description.abstract | A 1.35GHz all-digital phase-locked loop (ADPLL)
with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang-bang phase-frequency detector (BBPFD). The fractional divider partially compensates for the input phase error which is caused by the fractional-N frequency synthesis operation. A prototype ADPLL using a BBPFD with a dead zone free retimer, an ALGC, and a fractional divider is fabricated in 0.13m CMOS. The core occupies 0.19mm2 and consumes 13.7mW from a 1.2V supply. The measured RMS jitter was 4.17ps at a 1.35GHz clock output. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.title | A 1.35GHz All-Digital Fractional-N PLL with Adaptive Loop Gain Controller and Fractional Divider | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 김덕수 | - |
dc.contributor.AlternativeAuthor | 송희수 | - |
dc.contributor.AlternativeAuthor | 김태호 | - |
dc.contributor.AlternativeAuthor | 김수환 | - |
dc.contributor.AlternativeAuthor | 정덕균 | - |
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