SHERP

Schedule-Aware Performance Estimation of Communication Architecture for Efficient Design Space Exploration

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Authors
Kim, Sungchan; Im, Chaeseok; Ha, Soonhoi
Issue Date
2005-05
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Trans.Very Large Scale Integration systems, vol. 13, pp. 539-552, May. 2005
Keywords
Communication architecturedesign space explorationperformance estimationqueueing theory
Abstract
In this paper,we are concerned about performance estimation
of bus-based communication architectures assuming that
task partitioning and scheduling on processing elements are already
determined. Since communication overhead is dynamic and
unpredictable due to bus contention, a simulation-based approach
seems inevitable for accurate performance estimation. However,
it is too time-consuming to be used for exploring the wide design
space of bus architectures. We propose a static performance-estimation
technique based on a queueing analysis assuming that the
memory traces and the task schedule information are given. We
use this static estimation technique as the first step in our design
space exploration framework to prune the design space drastically
before applying a simulation-based approach to the reduced design
space. Experimental results show that the proposed technique
is several orders of magnitude faster than a trace-driven simulation
while keeping the estimation error within 10% consistently in
various communication architecture configurations.
ISSN
1063-8210
Language
English
URI
http://hdl.handle.net/10371/7438
DOI
https://doi.org/10.1109/TVLSI.2004.842912
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Computer Science and Engineering (컴퓨터공학부)Journal Papers (저널논문_컴퓨터공학부)
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