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Issue Date	Title / Author(s) / Citation	File
2019-06	Ge Condensation Process for High ON/OFF Ratio of SiGe Gate-All-Around Nanowire Tunnel Field-Effect Transistor Lee, Ryoongbin; Lee, Junil; Kim, Sangwan; Lee, Kitae; Kim, Sihyun; Kim, Soyoun; Choi, Yunho; Park, Byung-Gook 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), pp.51-52	DOI
2019-06	Sub-10 nm Advanced FinFET Design for Different Applications in Various Vdd and Temperature Operation Ranges Kim, Soyoun; Kim, S. K.; Kim, J. C.; Choi, B. H.; Park, B-G; Yasuda-Masuoka, Y.; Kwon, S. D. 2019 SYMPOSIUM ON VLSI TECHNOLOGY, pp.T108-T109	DOI
2020-06	Local Variation-Aware Transistor Design through Comprehensive Analysis of Various V-dd/Temperatures Using Sub-7nm Advanced FinFET Technology Kim, Soyoun; Kim, Seung Kwon; Yamaguchi, Taiko; Kim, Jae Chul; Park, Byung-Gook; Yasuda-Masuoka, Yuri; Kwon, S. D. 2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, p. 9265089	DOI