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Issue Date	Title / Author(s) / Citation	File
2019-08	Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization Jo, Kyeongrok; Ahn, Seyong; Do, Jungho; Song, Taejoong; Kim, Taewhan; Choi, Kyumyung IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.27 No.8, pp.1933-1946	DOI
2019-09	SRAM On-chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage Kim, Taehwan; Jeong, Kwangok; Kim, Taewhan; Choi, Kyumyung 2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019), pp.147-152	DOI
2022-06	Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon Heo, Jeongwoo; Jeong, Kwangok; Choi, Jung Yun; Kim, Taewhan; Choi, Kyumyung IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.41 No.6, pp.1929-1942	DOI