SRAM On-chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage

Abstract

Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, V-ddmin on each die that does not cause SRAM failure under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, V-fail that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM (V) over cap (ddmin) on each die from the measured V-fail of SRAM monitor on the same die where V-fail-V-ddmin correlation table is built-up in design infra development phase, and (V) over cap (ddmin), can he directly derived from the measured V-fail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 7.43%, read energy by 3.98%, and write energy by 4.06% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint.