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Issue Date	Title / Author(s) / Citation	File
2018-06	A 64 Gb/s 1.5 pJ/bit PAM-4 Transmitter with 3-Tap FFE and G(m)-Regulated Active-Feedback Driver in 28 nm CMOS Ju, Haram; Choi, Moon-Chul; Jeong, Gyu-Seob; Jeong, Deog-Kyoon 2018 IEEE SYMPOSIUM ON VLSI CIRCUITS, pp.51-52	DOI
2022-06	A 2.5 -32 Gb/s Gen 5-PCIe Receiver with Multi-Rate CDR Engine and Hybrid DFE Choi, Moon-Chul; Lee, Sanghee; Roh, Seungha; Lee, Kwangho; Oh, Jonghyun; Kim, Sungwoo; Kim, Kwandong; Choi, Woo-Seok; Kim, Jaeha; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.6, pp.2677-2681	DOI
2022-09	A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector Roh, Seungha; Lee, Kwangho; Shim, Minkyo; Choi, Moon-Chul; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.9, pp.3704-3708	DOI