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A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector

Cited 3 time in Web of Science Cited 3 time in Scopus
Authors

Roh, Seungha; Lee, Kwangho; Shim, Minkyo; Choi, Moon-Chul; Jeong, Deog-Kyoon

Issue Date
2022-09
Publisher
Institute of Electrical and Electronics Engineers
Citation
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.9, pp.3704-3708
Abstract
This brief presents a programmable phase detector (PD) for the Baud-rate clock and data recovery (CDR) in four-level pulse amplitude modulation (PAM-4) quarter-rate receiver, using a transition weighted gain (TWG) technique. By assigning a different gain to the phase detection for each data-level transition, the TWG-based CDR (TWG-CDR) achieves stable operation of the CDR and jitter tracking. An optimal phase detection transfer characteristic is obtained by assigning the highest weight on the 1-level data transition and the lowest on the 3-level transition. The proposed CDR fabricated in 40 nm CMOS technology performs at 64-Gb/s in PAM-4. The measured jitter tolerance (JTOL) shows that the TWG-CDR improves the horizontal eye opening margin compared to the sign-sign Mueller-Muller CDR. The TWG-CDR tested around a 6dB loss channel achieves a BER less than 10(-11) and energy efficiency of 2.37 pJ/b.
ISSN
1549-7747
URI
https://hdl.handle.net/10371/185623
DOI
https://doi.org/10.1109/TCSII.2022.3173429
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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