A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector

Abstract

This brief presents a programmable phase detector (PD) for the Baud-rate clock and data recovery (CDR) in four-level pulse amplitude modulation (PAM-4) quarter-rate receiver, using a transition weighted gain (TWG) technique. By assigning a different gain to the phase detection for each data-level transition, the TWG-based CDR (TWG-CDR) achieves stable operation of the CDR and jitter tracking. An optimal phase detection transfer characteristic is obtained by assigning the highest weight on the 1-level data transition and the lowest on the 3-level transition. The proposed CDR fabricated in 40 nm CMOS technology performs at 64-Gb/s in PAM-4. The measured jitter tolerance (JTOL) shows that the TWG-CDR improves the horizontal eye opening margin compared to the sign-sign Mueller-Muller CDR. The TWG-CDR tested around a 6dB loss channel achieves a BER less than 10(-11) and energy efficiency of 2.37 pJ/b.