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Issue Date	Title / Author(s) / Citation	File
2019-11	Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits Hyun, Gyounghwan; Kim, Taewhan 2019 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), p. 8942064	DOI
2019-11	Flip-flop State Driven Clock Gating: Concept, Design, and Methodology Hyun, Gyounghwan; Kim, Taewhan 2019 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), p. 8942061	DOI
2021-05	Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach Hyun, Gyounghwan; Kim, Taewahn IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.40 No.5, pp.892-903	DOI