Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits

Abstract

In this paper, we solve two critical limitations of the conventional approaches to the allocation of state retention storage for power gated circuits. Those are (1) the long wakeup delay caused by the senseless use of multi-bit retention flip-flops (MBRFF) and (2) the inability to optimize retention flip-flops for the flip-flops with mux-feedback loop. Note that the conventional approaches have regarded the long wakeup delay as an inevitable consequence of maximizing the reduction of total storage size for state retention while they have treated the flip-flops with self-loop as nonoptimizable component, but practically, the flip-flops with self-loop synthesized from HDL codes are not far from a small amount and thus, can in no way be negligible. Precisely, for solving (1), we show that the use of MBRFFs with up to two bits, consequently, constraining the wakeup delay to no more than two clock cycles, is enough to maintain the high reduction of total retention storage and for solving (2), we devise a 2-phase retention control mechanism for a pair of flip-flops, one of which has self-loop, by which just a single retention bit can be used to restore state of the two flip-flops, and propose an independent set based algorithm for maximally extracting the non-conflict pairs from circuits. Through experiments with benchmark circuits, it is shown that our proposed method is very effective, reducing the state retention storage by 9.8% on average over that produced by the existing best MBRFF allocation while the wakeup delay is strictly limited to two clock cycles as well as reducing the active and sleep power consumption by 4.52% and 11.03%.