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Issue Date	Title / Author(s) / Citation	File
2021-11	A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS Lee, Kwangho; Jung, Woosong; Ju, Haram; Lee, Jinhyung; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2021-11	Y A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS Ju, Haram; Lee, Kwangho; Jung, Woosong; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2022-06	A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation Kim, Hyojun; Jung, Woosong; Kim, Kwandong; Kim, Sungwoo; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Journal of Solid-State Circuits, Vol.57 No.6, pp.1712-1722	DOI
2022-09	A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing Yun, Daeho; Lee, Eonhui; Jung, Woosong; Kim, Kahyun; Beak, Kyung-Min; Kim, Jihee; Lee, Hyun-Bae; Ko, Byeongseon; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.9, pp.3749-3753	DOI