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A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation
Cited 3 time in
Web of Science
Cited 4 time in Scopus
- Authors
- Issue Date
- 2022-06
- Citation
- IEEE Journal of Solid-State Circuits, Vol.57 No.6, pp.1712-1722
- Abstract
- IEEEThis article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20-m ${{V}_{rms}}$ white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 mm², respectively.
- ISSN
- 0018-9200
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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