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A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Hyojun | - |
dc.contributor.author | Jung, Woosong | - |
dc.contributor.author | Kim, Kwandong | - |
dc.contributor.author | Kim, Sungwoo | - |
dc.contributor.author | Choi, Woo-Seok | - |
dc.contributor.author | Jeong, Deog-Kyoon | - |
dc.date.accessioned | 2022-08-25T01:15:25Z | - |
dc.date.available | 2022-08-25T01:15:25Z | - |
dc.date.created | 2022-05-11 | - |
dc.date.created | 2022-05-11 | - |
dc.date.created | 2022-05-11 | - |
dc.date.created | 2022-05-11 | - |
dc.date.issued | 2022-06 | - |
dc.identifier.citation | IEEE Journal of Solid-State Circuits, Vol.57 No.6, pp.1712-1722 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://hdl.handle.net/10371/184430 | - |
dc.description.abstract | IEEEThis article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20-m ${{V}_{rms}}$ white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 mm², respectively. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2022.3148174 | - |
dc.citation.journaltitle | IEEE Journal of Solid-State Circuits | - |
dc.identifier.wosid | 000757870800001 | - |
dc.identifier.scopusid | 2-s2.0-85124841487 | - |
dc.citation.endpage | 1722 | - |
dc.citation.number | 6 | - |
dc.citation.startpage | 1712 | - |
dc.citation.volume | 57 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Woo-Seok | - |
dc.contributor.affiliatedAuthor | Jeong, Deog-Kyoon | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordAuthor | All-digital phase-locked loop (ADPLL) | - |
dc.subject.keywordAuthor | Calibration | - |
dc.subject.keywordAuthor | Clocks | - |
dc.subject.keywordAuthor | closed-loop system | - |
dc.subject.keywordAuthor | digitally controlled resistor (DCR) | - |
dc.subject.keywordAuthor | Frequency modulation | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | multi-phase clock | - |
dc.subject.keywordAuthor | Phase locked loops | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | ring oscillator (RO) | - |
dc.subject.keywordAuthor | supply noise | - |
dc.subject.keywordAuthor | Transfer functions | - |
dc.subject.keywordAuthor | Voltage | - |
dc.subject.keywordAuthor | voltage headroom. | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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