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A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation

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dc.contributor.authorKim, Hyojun-
dc.contributor.authorJung, Woosong-
dc.contributor.authorKim, Kwandong-
dc.contributor.authorKim, Sungwoo-
dc.contributor.authorChoi, Woo-Seok-
dc.contributor.authorJeong, Deog-Kyoon-
dc.date.accessioned2022-08-25T01:15:25Z-
dc.date.available2022-08-25T01:15:25Z-
dc.date.created2022-05-11-
dc.date.created2022-05-11-
dc.date.created2022-05-11-
dc.date.created2022-05-11-
dc.date.issued2022-06-
dc.identifier.citationIEEE Journal of Solid-State Circuits, Vol.57 No.6, pp.1712-1722-
dc.identifier.issn0018-9200-
dc.identifier.urihttps://hdl.handle.net/10371/184430-
dc.description.abstractIEEEThis article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20-m ${{V}_{rms}}$ white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 mm², respectively.-
dc.language영어-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleA Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation-
dc.typeArticle-
dc.identifier.doi10.1109/JSSC.2022.3148174-
dc.citation.journaltitleIEEE Journal of Solid-State Circuits-
dc.identifier.wosid000757870800001-
dc.identifier.scopusid2-s2.0-85124841487-
dc.citation.endpage1722-
dc.citation.number6-
dc.citation.startpage1712-
dc.citation.volume57-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo-Seok-
dc.contributor.affiliatedAuthorJeong, Deog-Kyoon-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.subject.keywordAuthorAll-digital phase-locked loop (ADPLL)-
dc.subject.keywordAuthorCalibration-
dc.subject.keywordAuthorClocks-
dc.subject.keywordAuthorclosed-loop system-
dc.subject.keywordAuthordigitally controlled resistor (DCR)-
dc.subject.keywordAuthorFrequency modulation-
dc.subject.keywordAuthorJitter-
dc.subject.keywordAuthormulti-phase clock-
dc.subject.keywordAuthorPhase locked loops-
dc.subject.keywordAuthorphase noise-
dc.subject.keywordAuthorring oscillator (RO)-
dc.subject.keywordAuthorsupply noise-
dc.subject.keywordAuthorTransfer functions-
dc.subject.keywordAuthorVoltage-
dc.subject.keywordAuthorvoltage headroom.-
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