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Showing results 1 to 11 of 11

Issue Date	Title / Author(s) / Citation	File	Altmetrics
2013-06	A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR Shu, Guanghua; Saxena, Saurabh; Choi, Woo-Seok; Talegaonkar, Mrumnay; Inti, Rajesh; Elshazly, Amr; Young, Brian; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6578694
2014-02	8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS Shu, Guanghua; Choi, Woo-Seok; Saxena, Saurabh; Anand, Tejasvi; Elshazly, Amr; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.57, pp.150-151	DOI
2014-04	A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop Shu, Guanghua; Saxena, Saurabh; Choi, Woo Seok; Talegaonkar, Mrunmay; Inti, Rajesh; Elshazly, Amr; Young, Brian; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.49 No.4, pp.1036-1047	DOI
2014-06	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo-Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858446	DOI
2015-04	A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.882-895	DOI
2015-08	A 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS Saxena, Saurabh; Shu, Guanghua; Nandwana, Romesh Kumar; Talegaonkar, Mrunmay; Elkholy, Ahmed; Anand, Tejasvi; Kim, Seong Joong; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C352-C353	DOI
2016-02	A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Talegaonkar, Mrunmay; Anand, Tejasvi; Elkholy, Ahmed; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.51 No.2, pp.428-439	DOI
2016-02	A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b Source Synchronous Transceiver Using DVFS and Rapid On/Off in 65nm CMOS Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Nandwana, Romesh; Elkholy, Ahmed; Wei, Da; Nandi, Timir; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.59, pp.398-U558
2017-02	A 3-to-10Gb/s 5.75pJ/b Transceiver with Flexible Clocking in 65nm CMOS Nandwana, Romesh Kumar; Saxena, Saurabh; Elkholy, Ahmed; Talegaonkar, Mrunmay; Zhu, Junheng; Choi, Woo Seok; Elmallah, Ahmed; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.60, pp.492-493	DOI
2017-05	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver Saxena, Saurabh; Shu, Guanghua; Nandwana, Romesh Kumar; Talegaonkar, Mrunmay; Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.52 No.5, pp.1399-1411	DOI
2017-09	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS Talegaonkar, Mrunmay; Anand, Tejasvi; Elkholy, Ahmed; Elshazly, Amr; Nandwana, Romesh Kumar; Saxena, Saurabh; Young, Brian; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.52 No.9, pp.2306-2320	DOI

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