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Showing results 1 to 4 of 4

Issue Date	Title / Author(s) / Citation	File
2019-06	A 370-fJ/b, 0.0056 mm(2)/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop Ko, Han-Gon; Shin, Soyeong; Kye, Chan-Ho; Lee, Sang-Yoon; Yun, Jaekwang; Jung, Hae-Kang; Lee, Duobock; Kim, Suhwan; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C94-C95	DOI
2019-07	A Low-Power and Low-Noise 20:1 Serializer with Two Calibration Loops in 55-nm CMOS Jeong, Yong-Un; Chae, Joo-Hyung; Choi, Sungphil; Yun, Jaekwang; Jeong, Shin-Hyun; Kim, Suhwan 2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), p. 8824879	DOI
2020-10	A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45 degrees Strobe Phase for Energy-Efficient Skew Compensation Lee, Sangyoon; Ko, Han-Gon; Chae, Joo-Hyung; Shin, Soyeong; Yun, Jaekwang; Jeong, Deog-Kyoon; Kim, Suhwan IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.67 No.10, pp.1735-1739	DOI
2020-11	A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction Yun, Jaekwang; Lee, Sangyoon; Jeong, Yong-Un; Jeong, Shin-Hyun; Kim, Suhwan 2020 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), p. 9336144	DOI