A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction

Abstract

This paper proposes a fractional-N phase-locked loop (PLL) with a transition-detection DAC (TD-DAC) for jitter reduction. By introducing a TD-DAC, the sigma-delta modulator (SDM) quantization error of the PLL is compensated, and its overall jitter performance is improved. In order for the output frequency to cover the output frequency range of voltage controlled oscillator (VCO), the division ratio of the multi-modulus divider (MMD) is extended. Implemented in a 110nm CMOS process, the proposed fractional-N PLL dissipates 7.9mA from a 1.5V and 3.3V supply while occupying an area of 0.284mm(2). It operates over a frequency range of 0.4-1.7GHz, and a division range 4-4048. The prototype chip achieves an integrated RMS jitter of 3.78ps (100Hz to 40MHz), and the long-term jitter of it is 3.52ps(rms) and 22.1ps(pp).