S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Material Science and Engineering (재료공학부) Theses (Ph.D. / Sc.D._재료공학부)
Characterization of atomic layer deposited HfO2 and TiO2 high-k dielectrics on Si and Ge substrates
Si와 Ge 기판에서 원자층 증착법으로 증착한 HfO2와 TiO2 고유전막의 특성
- 공과대학 재료공학부
- Issue Date
- 서울대학교 대학원
- High-k; gate dielectric; Hafnium oxide; Titanium oxide; ALD; Atomic layer deposition; VFB modulation; O3 and H2O oxygen source; high mobility channel; Ge
- 학위논문 (박사)-- 서울대학교 대학원 : 재료공학부, 2014. 8. 황철성.
- The scaling of the CMOSFETs in silicon era which is using silicon dioxide has been already finished. Next generation CMOSFETs using HfO2 high-k gate dielectric have been particularly in the mass production as high-k gate dielectric. Atomic layer deposition has many advantages in the formation of gate dielectric thin films for extremely scaled planar or three-dimensional structured devices due to self-limiting growth behavior, which confirms a low leakage current, high dielectric constant, and atomic-level precise thickness control. However, more studies are required to solve the issues such as charge trapping, insufficient reliability, and the abnormally high threshold voltage (Vth) due to Fermi level pinning, and fabricate Hf-based dielectric films with even higher-k values (k > 30) for further scaled MISFETs (EOT < ~0.5 nm). In addition, there is a greater challenge to apply ALD-processed HfO2 to high-mobility channel materials such as III-V or II-V compound semiconductors for the n-type and Ge for the p-type MISFET. These challenges are known to be caused by the unstable interfaces between the HfO2 film and the high-mobility substrates, the status of which is largely influenced by the detailed ALD conditions. Several other high-k dielectrics have been adopted for the high-mobility substrates, but HfO2 is most favorable, can be extended to these substrates considering its mature process equipment, conditions, and contamination-control protocols in mass-production lines.
To control the abnormally high Vth value of Hf-based gate dielectrics, capping a rare earth metal oxide layer or Al2O3 on Hf based dielectrics have received great attention. The capping layer needs to be thin and uniform to achieve the desired Vth control effect over a wide wafer and not to increase the CET values. Therefore, one of the most promising approaches to modulate the Vth is to adopt ALD capping layers, which is being tipped off as a solution due to its superior thickness controllability and uniformity, along with no plasma damage.
The effects of the relative position and thickness of ALD grown Al2O3, SrO, and La2O3 capping layers with HfO2 gate dielectrics on flat band voltage (VFB) modulation of metal-insulator-semiconductor (MIS) capacitor is reported in this study. Atomic layer deposited Al2O3, SrO, and La2O3 capping layers with HfO2 gate dielectrics were examined. Al2O3 capping layers cause a VFB shift into the positive voltage direction, while SrO and La2O3 capping layers cause a shift into the negative voltage direction. The bottom capping layer, which positions between the Si substrate and the HfO2 dielectric was more effective in modulating the VFB compared to the top capping layer. The insulating properties of the gate dielectric stacks with different capping layers were also examined. X-ray photoelectron spectroscopy analysis verified that top capping layers did not generally diffuse to the interface between the Si substrate and the HfO2 dielectrics, which supports the result that bottom capping layers are more effective in modulating the VFB.
Variations in the growth behavior, physical and electrical properties, and microstructure of the atomic layer deposited HfO2 gate dielectrics were examined with two types of oxygen sources: O3 and H2O for the given Hf-precursor of Hf[N(CH3)(C2H5)]4. The ALD temperature windows for the O3 and H2O were 160-320oC and 160-280oC, respectively, with the growth rate of HfO2 using O3 being higher than that of the films using H2O within the ALD window. While the film density of HfO2 using O3 decreased, that of HfO2 using H2O increased with the decreasing ALD temperature. As the deposition temperature decreased, the amount of impurity in the HfO2 film with the O3 oxygen source increased due to the insufficient reaction, which led to the crystallization of the HfO2 film into the tetragonal structure after the post-deposition annealing at 600oC. The films with a lower density and a higher carbon-impurity concentration retained the portion of the tetragonal phase (~30%) to the highest annealing temperature of 1000oC. However, the HfO2 films grown at 200oC with H2O showed the best electrical performance, which could be ascribed to the highest density, low impurity concentration, and negligible involvement of the interfacial low dielectric layer.
HfO2 films using O3 and H2O oxygen source at different deposition temperature applied to high-mobility substrates Ge. H2O oxygen source could reduce the formation of sub-oxide at interface between HfO2 and substrate. However, H2O has weaker oxization power than O3, impurities such as carbon is residued in deposited film which can act as defects. SiO2, Al2O3 passivation layer improved the leakage current and passivation of reaction or intermixing at interface between HfO2 and substrate.
There was a limit to improve using HfO2 high-k dielectric on high mobility substrate, it is essential to insert the passivation layer at interface which has low k value. Therefore TiO2 of higher k value was adopted which have even small band gap with low barrier with Si and Ge substrates. SiO2 and SiON passivation layer were effectively reduced the hysteresis voltage, frequency dispersion, and interface trap density. For more scaling the CET, the thickness of SiO2 passivation layer was decreased from 2 to 0.5nm with TiO2 high-k oxide. Dit values were maintained in order of 1011 level until 1nm of SiO2 thickness
it is degraded in the condition of 0.5nm of SiO2 thickness. At least 1nm of SiO2 thickness is required for passivation the surface of Ge substrate. The EOT was scaled up to 1.4nm, Dit value was decreased as 1.3x1011cm-2eV-1.