A Study of Bottom Gate MILC Polycrystalline Silicon TFTs and Reduction of the Leakage Current

Abstract

Nowadays the display market meets the transitional period of change. In the past decade, the main stream of display market is move from Cathode Ray Tube (CRT) to Liquid Crystal Display (LCD) and now, it is move from LCD to Active Matrix Organic Emitting Diode (AMOLED). The main reason of this transition is due to the requirement of extremely high resolution display and need of the advanced display for example the transparent and foldable display. The LCD which is the most basic devices among the flat panel displays, use amorphous silicon Thin Films Transistor (TFT) in order to control the each pixels. Even if the field effect mobility of amorphous silicon TFTs is less than 1 cm2/Vs, it is high enough to operate the LCD because LCD is voltage controlled device. However, unlike with LCD, the AMOLED needs high field effect mobility because of current controlled device. So, polycrystalline silicon TFTs should be used for AMOLED display. Among the several method of crystallization, we used the Metal Induced Lateral Crystallization (MILC) for phase transform from amorphous to polycrystalline. In the structure point of view, the LCD have to use bottom gate structure, because of light exposure from back side, so bottom electrode could block the light at the channel inversion layer. Otherwise, AMOLED have to use top gate structure, because of the crystallization process. The Excimer Laser Annealing (ELA) method is widely used for crystallization in commercial area. The bottom gate structure could not be used for ELA process, because of bottom electrode twisted and damaged. In order to use LCD manufacturing line for making AMOLED, polycrystalline silicon bottom gate structure must be fabricated. Therefore, in this experiment, we focus on the fabrication of bottom gate MILC polycrystalline silicon TFTs and its electrical properties. The first step for bottom gate structure is the crystallization of Plasma Enhanced Chemical Vapor Deposition (PECVD) amorphous silicon layer. Low Pressure Chemical Vapor Deposition (LPCVD) amorphous silicon layer could be crystallized in hydrogen ambient. However, the PECVD amorphous silicon layer could not be crystallized in hydrogen ambient annealing. The main difference between PECVD and LPCVD amorphous silicon layer is silicon hydrogen bonding configuration. Using Fourier Transform Infrared Spectroscopy (FT-IR), the silicon-hydrogen bonding configuration is measured. The PECVE has Si-H bonding and LPCVD has Si-H3 bonding. The Si-H bonding is more stable than Si-H3 bonding, so in furnace annealing LPCVD has faster crystallization ratio than PECVD layer. And the binding energy of silicon-hydrogen is lower than silicon-nickel (nickel metal is widely used for metal catalyst). In hydrogen ambient, the silicon atoms are easily connected with hydrogen, so the lateral growth rate is much slower in hydrogen ambient. So, lateral crystallization of PECVD silicon layer is obtained in vacuum condition furnace annealing. We could fabricate the bottom gate MILC polycrystalline silicon TFTs using PECVD silicon layer in vacuum furnace annealing. However, because of metal silicide and metal contamination in silicon layer, relatively high leakage current level is main drawback of MILC polycrystalline silicon. In order to reduce the leakage current, we applied two types of novel structure. The first one is called Overlap/off-set structure. Overlap/off-set structure is describe that the vertically overlap region between bottom gate electrode and doped source/drain area. With this structure, the leakage current is decreased due to the depletion region under reverse bias gate voltage. Second structure is Direct/Indirect junction which is represented the contact between doped source/drain and channel inversion layer. With indirect junction structure, the leakage current is reduced because of reduction of tunneling process. With direct junction structure both on current and off current is higher than indirect junction. The mechanism of on current differs to that of leakage current. The on current is the result of carrier movement from source to drain passing by the channel inversion layers. And the leakage current is also the flow of carriers, but the carriers are generated not only from the source or drain region but also from defect states such as the metal silicide defect center. Normally, the leakage current occurs by three types of mechanisms: thermal activation, generation from the defect center in the middle of the band gap, and tunneling. With wide depletion region, the tunneling current is reduce mainly. In conclusion, in this research, we could fabricate the bottom gate structure MILC polycrystalline silicon TFTs and applied novel structure for reducing leakage current which is called overlap/off-set and direct/indirect junction structure.