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Advanced Device Architectures for Organic Logic Elements and Nonvolatile Memory Cells : 유기 논리 소자와 비휘발성 메모리를 위한 고성능 소자 구조

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dc.contributor.advisor이신두-
dc.contributor.author김민회-
dc.date.accessioned2017-07-13T06:56:03Z-
dc.date.available2017-07-13T06:56:03Z-
dc.date.issued2013-02-
dc.identifier.other000000008476-
dc.identifier.urihttps://hdl.handle.net/10371/118879-
dc.description학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 이신두.-
dc.description.abstractOrganic electronics has attracted much attention due to their low-cost, large-area, and flexible electronic device applications such as flexible displays, radio frequency identification tags, and sensor sheets. Especially, numerous approaches for the high performance organic thin-film transistors (OTFTs) have been studied due to their driving and switching capability. Recently, for the commercialization of the OTFTs, not only a single device but electronic functional blocks which consist of various types of OTFTs are studied. One of the great ways to obtain both high performance of single device and integration of various OTFTs is to design new device architectures. In order to fabricate new device structures, new patterning process is required, since the conventional patterning process such as photolithography cannot be used for organic materials due to the damage of organic materials during photolithography.
In this thesis, new device physics and process technology of the advanced device architectures are presented for the enhancement of the performance of the single OTFT and the realization of the electronic functional blocks. Especially, it is presented that the underlying physical mechanism comes from the interface between the gate insulator and the organic semiconductor. First, the general overview of the organic electronics and the operation principles of the OTFTs are introduced. It is demonstrated how the parameters of the OTFTs, organic inverters, and ferroelectric OTFTs affect the device performance.
In the viewpoint of the single device, it is presented how device architectures have an influence on the performance of the OTFTs. In order to obtain saturated high drain current at low voltage, the chevron gate configuration is designed and fabricated. Furthermore, the short channel effect and current modulation is physically analyzed. For the high performance OTFTs with the n-type polymer semiconductor, the dual-gate architecture is introduced. The dual-gate architecture allows the threshold voltage and mobility to be controlled by the biasing the counter gate electrode.
Next, combination of the two different types of the OTFTs for the novel electronic functional blocks is demonstrated. The interface between First, the control mechanism for interfacial charges in an OTFT by the introduction of a surface polarized layer (SPL), which generates a transverse dipolar field, is demonstrated. The concept of such SPL enables to develop a high noise-margin full-swing unipolar inverter on a single substrate. The transverse dipolar field of the SPL of a fluorinated polymer which is placed between the organic semiconductor and the gate insulator plays an essential role in the accumulation of holes at the interface due to the surface dipoles of the fluorinated polymer. Owing to the interfacial holes, the OTFT with the SPL operates in a depletion mode and its magnitude lies between the on-current and off-current of a conventional OTFT with no SPL. This directly allows the high noise-margin and the full-swing capability of an organic unipolar inverter with zero gate load OTFT.
Second, paraelectric/ferroelectric bilayer architectures in ferroelectric OTFT for nonvolatile memory array are demonstrated. The paraelectric buffer layer (PBL) on the ferroelectric layer plays an essential role in screening the electric field of the ferroelectric dipole and reducing the roughness of the insulator. It is found that the OTFTs with the bilayer structure exhibit high switching on-off current ratio and low memory on-off current ratio. Through the selective formation of the bilayer structure, the ferroelectric memory OTFTs are integrated with the selection OTFTs having the bilayer structure. Through this configuration, ferroelectric memory array without crosstalk between memory cells and voltage-readable multistate ferroelectric memory cell are demonstrated.
In conclusion, through this thesis, it is presented that the advanced device architectures enhanced the performance of the single device and realized the electronic functional blocks. Approaches of increasing the drain current and controlling the threshold voltage, introduced here, are expected to provide a basis for realizing many applications of the OTFTs. Moreover, the device physics and the integration technique for the organic inverter and ferroelectric circuit will provide a platform for the organic logic elements and nonvolatile memory cells.
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dc.description.tableofcontentsChapter 1 . Introduction 1
1.1 Organic Electronics 1
1.2 Organic Thin-Film Transistor 3
1.2.1 Operation of organic thin-film transistor 3
1.2.2 Organic inverter 7
1.2.3 Ferroelectric organic thin-film transistor 9
1.3 Outline of Thesis 11
Chapter 2 . Functional Organic Thin-Film Transistor 13
2.1 Short Channel OTFTs for High Drain Current 13
2.1.1 Introduction 13
2.1.2 Chevron gate configuration 16
2.1.3 Thin Self-grown AlOX 21
2.1.4 Electrical characteristic of short channel chevron OTFT 25
2.1.5 Summary 30
2.2 N-type Dual-Gate OTFT for Threshold Voltage Control 31
2.2.1 Introduction 31
2.2.2 Fabrication of dual-gate configuration 32
2.2.3 Electrical characteristic of dual-gate OTFT 34
2.2.4 Threshold voltage control of dual-gate OTFT 36
2.2.5 Summary 40
Chapter 3 . Organic Logic Elements 41
3.1 Introduction 41
3.2 Tranfer-Printing of SPL 44
3.2.1 Process of transfer-printing 44
3.2.2 Morphological propeties of SPL and pentacene films 47
3.3 Electrical Characteristics of SPL Capacitors and OTFTs 49
3.3.1 Turn-on voltage shift 49
3.3.2 Thickness independence of SPL 55
3.4 Full-Swing Oanic Inverter 57
3.5 Summary 60
Chapter 4 . Nonvolatile Memory Cells 61
4.1 Introduction 61
4.1.1 Array of ferroelectric memory 63
4.1.2 Multi-level voltage-readable memory 65
4.2 Fabrication of Ferroelectric Memory Circuit 68
4.2.1 Process of fabrication 68
4.2.2 Morphological properties of PBL 71
4.3 Effect of PBL on Ferroelectric OTFTs 73
4.4 Ferroelectric Memory Array 77
4.5 Intermediate States of Ferroelectric OTFT 79
4.6 Voltage-Readable Multistate Ferroelectric Memory 83
4.7 Summary 86
Chapter 5 . Concluding Remarks 87
Bibliography 90
Publications 98
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dc.formatapplication/pdf-
dc.format.extent3299323 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subjectorganic thin-film transistor-
dc.subjectinterfacial interactions-
dc.subjectchevron gate configuration-
dc.subjectdual gate-
dc.subjectorganic inverter-
dc.subjectferroelectric nonvolatile memory-
dc.subject.ddc621-
dc.titleAdvanced Device Architectures for Organic Logic Elements and Nonvolatile Memory Cells-
dc.title.alternative유기 논리 소자와 비휘발성 메모리를 위한 고성능 소자 구조-
dc.typeThesis-
dc.contributor.AlternativeAuthorMin-Hoi Kim-
dc.description.degreeDoctor-
dc.citation.pages111-
dc.contributor.affiliation공과대학 전기·컴퓨터공학부-
dc.date.awarded2013-02-
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