Design of All-Digital PLL Using Statistical Data of Bang-Bang Phase Detection

Abstract

An all-digital phase-locked loop (ADPLL) and an all-digital spread spectrum clock generator (SSCG) are proposed using the stochastic data of the bang-bang phase-frequency detection. The all-digital bang-bang PLL (BBPLL) that tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the output of bang-bang phase frequency detector (BBPFD) indicates whether the BBPLL operates in the nonlinear regime or the random noise regime. Using the behavioral model simulation and mathematical analysis, it is shown that the output jitter is minimized when the autocorrelation of BBPFD output is zero. An adaptive loop gain controller (ALGC) continuously evaluates the autocorrelation of the BBPFD output and adjusts the loop gain to make the autocorrelation zero. The digital loop filter (DLF) operates at higher than the reference clock frequency to reduce the loop latency and to mitigate the resolution of the digitally-controlled oscillator (DCO). The prototype chip has been fabricated in a 65-nm CMOS process. It exhibits rms jitter of 1.72 ps at 2.5 GHz. The all-digital SSCG using two-point modulation is presented. To calibrate the gain mismatch between the direct and division ratio modulation paths, a background gain calibration method is proposed. An adaptive gain controller (AGC) continuously evaluates the correlation between the modulation profile and the BBPFD output and adjusts the direct modulation gain to make the correlation zero. To reduce the power consumption and design complexity, the BBPFD is used instead of the time-to-digital converter (TDC). The prototype chip has been fabricated in a 65-nm CMOS process and it consumes 6 mW at 2.5 GHz. The measured minimum rms jitter is 1.58 ps.