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GIDL characteristics on Si1-xGex pFinFET for Low Power Transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 신형철 | - |
dc.contributor.author | 강덕승 | - |
dc.date.accessioned | 2017-07-13T07:14:47Z | - |
dc.date.available | 2017-07-13T07:14:47Z | - |
dc.date.issued | 2016-02 | - |
dc.identifier.other | 000000133122 | - |
dc.identifier.uri | https://hdl.handle.net/10371/119181 | - |
dc.description | 학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 신형철. | - |
dc.description.abstract | This dissertation presents an investigation of Gate-Induced-Drain-Leakage (GIDL) current in SiliconGermanium (SiGe) p-type FinFET for low power transistors and proposes the guidelines to reduce GIDL current. First, the main mechanism of GIDL current in FinFET was thoroughly investigated because conventional GIDL current is unexpected event in FinFET. Therefore, GIDL current in FinFET is analyzed by comparing that in MOSFET which has the same device specification as the FinFET. Second, the effects of Ge fraction and its distribution in internal fin on GIDL current were analyzed considering actually manufactured fin in SiGe FinFET. Third, the analysis of GIDL current by the device specifications and doping profile in drain region was presented. As a result, guidelines are presented considering the results above. The main mechanism and the characteristics of GIDL current in FinFET which are investigated in this dissertation would be and index to improve the characteristics of manufactured SiGe FinFET. | - |
dc.description.tableofcontents | Chapter 1. Introduction 1
1.1. Multigate MOSFET 1 1.2. SiliconGermanium (SiGe) characteristics 4 1.3. Scope and Organization 7 Chapter 2. Gate-Induced-Drain-leakage current in FinFET 8 2.1. Introduction 8 2.2. Modeling of GIDL current 12 2.3. Comparison of GIDL between MOSFET and FinFET 16 2.4. Summary 28 Chapter 3. Effects of device specifications on GIDL 29 3.1. Introduction 29 3.2. Effects of Ge fraction in Si1-xGex pFinFET on GIDL 30 3.3. Effects of manufacturing process conditions on GIDL 41 3.4. Effects of doping profile on GIDL 49 3.5. Junction depth under the drain region 58 3.6. Summary 63 Chapter 4. Optimization of Si1-xGex pFinFET for low-power transistor 64 Chapter 5. Conclusion 68 Appendix A. Leakage current by strain engineering 70 A.1. Introduction 70 A.2. Effect of interface traps on leakage current 72 A.3. Effect of band-gap on leakage current 75 A.4. Conclusion 77 Abstract in Korean 90 | - |
dc.format | application/pdf | - |
dc.format.extent | 1820348 bytes | - |
dc.format.medium | application/pdf | - |
dc.language.iso | en | - |
dc.publisher | 서울대학교 대학원 | - |
dc.subject | SiliconGermanium | - |
dc.subject | finFET | - |
dc.subject | GIDL | - |
dc.subject | TCAD simulation | - |
dc.subject.ddc | 621 | - |
dc.title | GIDL characteristics on Si1-xGex pFinFET for Low Power Transistors | - |
dc.type | Thesis | - |
dc.description.degree | Doctor | - |
dc.citation.pages | 90 | - |
dc.contributor.affiliation | 공과대학 전기·컴퓨터공학부 | - |
dc.date.awarded | 2016-02 | - |
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