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Design of an Efficient Capacitor-Free Piezoelectric Energy Harvesting PMIC
저장 커패시터를 가지지 않는 효율적인 압전소자 에너지 하베스팅 전력관리 회로 설계

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Authors
양준석
Advisor
김재하
Major
공과대학 전기·정보공학부
Issue Date
2016-08
Publisher
서울대학교 대학원
Keywords
에너지 하베스팅
Description
학위논문 (석사)-- 서울대학교 대학원 : 전기·정보공학부, 2016. 8. 김재하.
Abstract
This research suggests a design methodology of an efficient piezoelectric power management IC which removes the large intermediary buffer capacitor and achieves a high end-to-end energy efficiency that can theoretically be 100%. A prototype IC designed and simulated on a 0.18-μm HVCMOS process showed 460% enhancement on the case of continuous input vibration with respect to the full-bridge diode topology, and showed 61% end-to-end efficiency for a batteryless wireless switch application which is 1.7 times higher than the ideal efficiency of a capacitor-based topology.
Language
English
URI
https://hdl.handle.net/10371/122832
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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