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Power Optimization Techniques Applicable in Pre/Post Placement Stages for Modern System-on-Chips
최신 System-on-Chip에서의 Placement 전/후 파워 최적화 기법

DC Field Value Language
dc.contributor.advisor김태환-
dc.contributor.author이동윤-
dc.date.accessioned2017-07-14T02:45:01Z-
dc.date.available2017-07-14T02:45:01Z-
dc.date.issued2017-02-
dc.identifier.other000000142435-
dc.identifier.urihttps://hdl.handle.net/10371/122862-
dc.description학위논문 (석사)-- 서울대학교 대학원 : 전기·정보공학부, 2017. 2. 김태환.-
dc.description.abstractIn this paper, we introduce two power optimization techniques applicable before and after placement stage.
First, a new approach to the problem of allocating multi-bit flip-flops for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) placing single-bit flip-flops under circuit timing constraints and (ii) minimizing the flip-flop and clock tree power by grouping single-bit flip-flops to form multi-bit flip-flops. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of power consumption. Consequently, we try to minimize power consumption by synthesizing multi-bit flip-flops first and then to place them later. For a number of benchmark circuits, it is shown that our approach of early consideration of synthesizing multi-bit flip-flops is very effective, reducing the clock power by 16.8% over that of the conventional method while satisfying all the timing constraints.
The second work addresses a practical problem of optimizing the switch cells in power-gated modern System-on-Chips (SoCs) to save the unnecessary standby leakage under noise (i.e., IR-drop) constraint. Since power gating switch cells are physically directly connected to power rails, their overall allocation structure is synthesized in a stage before logic cell placement. Consequently, the allocation of switch cells in the pre-placement could lead to unnecessarily high standby leakage for modern designs. This work proposes a practical remedy for this problem at the post-placement stage. Specifically, for an initial design with a grid-based switch cell allocation, which is commonly used design methodology in industry, we propose a comprehensive solution to determining, for each switch cell, (i) if the cell can be removed or (ii) the type of switch cell for replacement so that the resulting total standby leakage of switch cells should be minimized under the noise constraint.We formulate the problem into a variant of weighted set cover problem and solve it efficiently by employing an approximate set cover algorithm. Through experiments with benchmark circuits in ISCAS89, openMSP430, and fpu, it is shown that our method is able to reduce the standby leakage by 35.0% and 13.9% over the initial designs and the designs produced by the previous switch cell optimization method in [9], respectively.
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dc.description.tableofcontents1 Allocation of Multi-bit Flip-flops in Logic Synthesis for Power Optimization 1
1.1 Introduction 1
1.2 Algorithm for Multi-bit Flip-flop Allocation 3
1.3 Placement Aware Multi-bit Flip-flop Allocation 6
1.3.1 Extraction of Mergeable Flip-flop Sets 6
1.3.2 Construction of Merging Conflict Graph 9
1.3.3 Selection of Mergeable Flip-flop Sets 9
1.4 Experimental Results 11
1.4.1 Experimental Setup 11
1.4.2 Comparing with Academic Algorithm 14
1.4.3 Comparing with Industry Algorithm 16
1.5 Conclusion 17
2 Switch Cell Optimization of Power-gated Modern System-on-Chips 18
2.1 Introduction 18
2.2 Preliminaries and Motivations 21
2.3 Problem Formulation 24
2.4 The Proposed Algorithm 25
2.4.1 Extraction of Maximally Feasible Subregions 25
2.4.2 Switch Cell Covering for Minimal Standby Leakage 28
2.4.3 Consideration of Practical Issues 32
2.5 Experimental Results 34
2.5.1 Experimental Setup 34
2.5.2 Experimental Result 35
2.6 Conclusions 38
Bibliography 39
초록 42
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dc.formatapplication/pdf-
dc.format.extent4909243 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subjectLow power-
dc.subjectMulti-bit Flip-flop-
dc.subjectSynthesis-
dc.subjectPower-gating-
dc.subjectSwitch cell-
dc.subject.ddc621-
dc.titlePower Optimization Techniques Applicable in Pre/Post Placement Stages for Modern System-on-Chips-
dc.title.alternative최신 System-on-Chip에서의 Placement 전/후 파워 최적화 기법-
dc.typeThesis-
dc.contributor.AlternativeAuthorDongyoun Yi-
dc.description.degreeMaster-
dc.citation.pages43-
dc.contributor.affiliation공과대학 전기·정보공학부-
dc.date.awarded2017-02-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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