Analysis of dependence on oxide traps location of RTN in GIDL current of DRAM cell transistors : DRAM 셀 트렌지스터의 GIDL RTN에 의한 산화막 트랩의 위치 의존성 분석

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Shin Hyungcheol
공과대학 전기·컴퓨터공학부
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서울대학교 대학원
학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. Shin Hyungcheol.
As device dimensions are minimized, random telegraph noise (RTN) is dominant in determining the performance and reliability of metal-oxide-semiconductor field effect transistor (MOSFET). The origin of RTN is attributed to trapping/de-trapping of carriers in trap located in a gate oxide or at a Si/SiO2 interface. Until now, most research on the characterization of an oxide trap investigates for the channel or gate leakage current and a few for gate-induced drain leakage current, a significant leakage component of current in modern MOSFETs which is mainly associated with both band-to-band or trap-assisted-tunneling in a gate to drain overlapped region. As a result, RTN in GIDL current is believed to be a cause of variable retention time in DRAM devices. Due to those reasons, there has been much interest regarding RTN in GIDL current. Previous authors have reported that oxide traps cause RTN in GIDL current from experimental work. For better understanding of characterization of oxide traps that lead to fluctuations of GIDL current, it is necessary to obtain accurate information about the characterization of these traps.
In this thesis, we have developed an accurate model to represent the variation of GIDL current which depends on location of an oxide trap by all vertical, lateral and width direction, and expected the traps position at the gate oxide. We also analyzed the amplitude of RTN in GIDL current as a function of the drain to gate voltage. Also, we investigated the characterization of the oxide trap with 20-nm Saddle MOSFET, a promising candidate for DRAM high-density applications.
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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